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College of Engineering

 

Shantanu Dutt
Professor

Contact Information
312.355.1314
312.996.6465(fax)
851 S. Morgan M/C 154
Chicago, IL. 60607
dutt[at]ece[dot]uic[dot]edu
Education
Ph.D. Computer Science and Engineering
University of Michigan, Ann Arbor 1990
M.Tech. in Computer Engineering
Indian Institute of Technology, Kharagpur, India 1984.
B.E. Electronics and Communication Engineering
Maharaja Sayajirao University of Baroda, Baroda India, 1983
 
Professional Achievements
   
  Best paper award nomination for the paper ``Efficient On-Line Testing of
FPGAs with Provable Diagnosabilities'', at the Design Automation
Conference, June 2004 , a premier conference for VLSI CAD and testing.
 
 
  Best Paper award for the paper ``A probability-based approach to VLSI
circuit partitioning", at the ACM/IEEE Design Automation Conference, Las
Vegas, June 1996.
 
 
Most influential paper award for the paper ``Design and reconfiguration
strategies for near-optimal k-fault-tolerant tree architectures" at the
Fault Tolerant Comput. Symp., 1995 (for a paper that appeared in FTCS'88).
 
 
Research Initiation Award from NSF for "Efficient Design of
Fault-Tolerant Multiprocessors", 9/92 - 2/96.
 
Invited article: S. Dutt, F. Rota, F. Trovo and F. Hanchek, ``Fault
Tolerance in Computer Systems--From Circuits to Algorithms", invited
article, in Electrical Engineering Handbook, Academic Press, 2004.
 
 
Invited article: S. Dutt and D. Boley, ``Roundoff Errors", invited
article, in Wiley Encyclopedia of Electrical and Electronics Engineering,
Vol. 18, 1999, pp. 617-627.
 
Invited paper: N.R. Mahapatra and S. Dutt, ``New anticipatory
load balancing strategies for scalable parallel best-first search",
DIMACS workshop on Parallel Processing of Discrete Optimization
Problems, April 1994.
 
   
Research Interests  
 
Computer-Aided design of FPGA and VLSI circuits (physical design, physical synthesis, logic synthesis, high-level synthesis, timing and power-driven design tools with temperature considerations), combinatorial optimization, fault-tolerant computing—systems and chips, trust and security in VLSI chips and computer systems, FPGA testing, and parallel computing.
 
 
 
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